1. Field of the Invention
The invention generally relates to roughened metal surfaces that can be used, for example, in integrated circuits. More particularly, methods for depositing roughened thin films and particles and controlling the roughness of metal thin films are provided, along with structures incorporating such films and particles.
2. Description of the Related Art
When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned layer by layer. Many types of circuits incorporate capacitors, each of which includes a dielectric layer sandwiched between two plates (or electrodes). Memory chips such as dynamic random access memories (DRAMs), in particular, employ capacitors to store charge in memory cells. Each memory cell can represent one bit of data, where the capacitor can either be charged or discharged to represent logical states.
In accordance with the general trend in the semiconductor industry, integrated circuits are continually being reduced in size in order to achieve higher processing speeds and lower power consumption. Because a capacitor in a memory cell of a memory chip must store a certain minimum charge, to ensure reliable operation of the memory cell without the need for excessive refresh cycling, with IC size reduction and concomitant increase in packing density of memory chips, it is important that capacitors be able to store more charge per area of the chip (or footprint) allotted to each cell. Techniques have been developed to increase the total charge capacity of the cell capacitor for a given footprint.
The amount of charge stored on the capacitor is proportional to the capacitance, C=kk0 A/d, where ‘k’ is the permittivity (or dielectric constant) of the dielectric material between the two electrodes of the capacitor, ‘k0’ is the vacuum permittivity, ‘A’ is the effective surface area of the electrodes, and ‘d’ is the spacing between the electrodes, also representing the thickness of the inter-electrode dielectric.
Rather than relying solely upon the height (or depth) of the cell capacitor, techniques have focused on increasing the effective surface area (A) of the electrodes by creating folding structures for stacked capacitors or trench capacitors. Trench capacitors are formed within the semiconductor substrate in which transistors are typically formed, whereas stacked capacitors are formed above the transistors. Such structures better utilize the available chip area by creating three-dimensional shapes which the conductive electrodes and capacitor dielectric conform to.
As an alternative, a microstructure can further increase the effective surface area of the capacitor electrodes by providing a textured or roughened surface to the macrostructural folds of the lower electrode. For example, polycrystalline conductive materials can be roughened by preferentially etching along grain boundaries, as disclosed, for example, in U.S. Pat. No. 3,405,801, issued to Han et al. Alternatively, U.S. Pat. No. 5,372,962, issued to Hirota et al., describes various selective etch processes for perforating a polysilicon layer.
Another class of electrode texturing techniques involves forming hemispherical grained (HSG) silicon. Several methods for forming HSG silicon are known, including direct deposition, whereby deposited polysilicon selectively grows over nucleation sites, and redistribution annealing of amorphous silicon, whereby thermal energy causes silicon atoms to migrate across a surface and agglomerate at distinct nucleation sites.
Traditionally HSG electrodes have consisted of polysilicon material, which suffers from depletion effects, thereby increasing the effective oxide thickness (EOT) typically by about 3-5 Å or more. By replacing polysilicon with a metal or a metallic compounds (or other electrically conductive material), the depletion effect can be avoided. Noble metals, such as ruthenium, are leading candidates for the electrodes of metal-insulator-metal (MIM) capacitors.